1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) cell and a method for making the same, and more particularly to a trench silicon-on-insulator (SOI) DRAM cell and a method for making the same.
2. Description of the Related Art
Semiconductor technology is developing towards devices and systems with small volume, low power consumption, low leakage current, and high operating speed. As for a semiconductor memory, a conventional DRAM is a memory cell composed of a transistor and a capacitor. As the demand for a larger memory capacity increases, people attach more importance to the integration density of the memory. Although transistors have been miniaturized to allow mass production under 65 nm in recent years, in a conventional bulk metal-oxide semiconductor (MOS) structure, the integration density of the DRAM cell is limited by the capacitor size, and cannot be increased significantly.
Recently, many DRAM cell techniques concerning stack capacitors (referring to ROC Patent No. 465015) and trench capacitors (referring to U.S. Pat. No. 6,426,252 B1 and ROC Patent No. 1270179) have been proposed. In these techniques, though a capacitor board area is increased in a limited space, it is still quite complicated to make an electrode and a dielectric layer with high quality in a structure with a large depth-to-width ratio. Therefore, effectively reducing the area occupied by the capacitor in the DRAM is a problem that needs to be solved in the industry, and the most direct and most common solution is to fabricate the transistor on a trench capacitor.
However, as the transistor size is reduced, during the performance of the memory, parasitic capacitance and short channel effect problems may occur, which are as important as the integration density of the memory. Therefore, research in which a bulk MOS device is replaced by an SOI is proposed (referring to ROC patent No. 1267979). The SOI device applied to the DRAM has the following advantages. 1. The device has a relatively smaller drain-body and source-body parasitic capacitance, so as to increase the charging and discharging speeds. 2. The device has better short channel effect immunity. 3. The device may effectively prevent the DRAM from being damaged by radiation which would generate soft errors.
Currently, the research on the SOI-DRAM is moving towards a capacitor-less memory. For example, for a partially depleted SOI (PDSOI)-DRAM, the capacitor function is replaced by the electric charge in a pseudo neutral region of the device body based on a floating body effect, that is, a 1T-DRAM structure is used to most effectively solve the problem that the conventional 1T-1C-DRAM occupies too much area.
However, the pseudo neutral region is affected by doping concentration, source/drain junction depth, and body thickness, so the stored electric charge may not be large enough to be sensed by a circuit of a sensing amplifier, which is the most difficult problem of the 1T-DRAM. Currently, it is considered that the stored electric charge may be increased by using a back gate or by increasing the body thickness. However, the back gate structure undoubtedly increases the complexity and the reliability of the device, and the greater body thickness relatively increases the parasitic capacitance, which lowers the charging and discharging speeds of the memory.
In addition, in the SOI-DRAM provided in ROC Patent No. 1267979, the trench structure is still a capacitor board structure with a high depth-to-width ratio and a high complexity.
Therefore, it is necessary to provide a trench SOI-DRAM cell and a method for making the same, so as to solve the above problems.